As microprocessors become faster and smaller, integrated circuitry (IC) becomes more complex and components become more densely packed. The use of non-planar fin based transistor devices has enabled increased performance with a smaller device footprint. Fins that are substantially rectangular in shape have improved short channel effects compared to fins with trapezoidal or triangular shapes. This leads to higher performance for a given voltage overdrive. Rectangular fins also enable consistent device performance across the fin height with no degradation in current.
However, as the aspect ratio of transistor devices continues to increase, the challenge of maintaining uniform widths and rectangular cross-sections of the fins across the substrate becomes more difficult. Specifically, when the critical dimension (CD) and pitch of the devices decrease, micro loading effects become a significant problem. Micro loading effects occur when the CD and pitch of the fins is small enough to create different active ion accessibility at the surface of the substrate during an etching process. This results in a structurally dependent etch bias due to localized enhanced etching or plasma deposition. Additionally, the micro loading effect becomes a more significant problem when the pitch between fin based structures is non-uniform. As an example, when nested fins and isolated fins are formed with a single etching process, the widths of the nested fins will not be equal to the widths of the isolated fins, because the micro loading effect will be different for each type of fin. Accordingly, it becomes increasingly difficult to design circuitry that includes fin based transistor devices that require non-uniform spacing. As a result of the different pitches, nested fins will have different metrics, such as leakage current and threshold voltage, than isolated fins, even though both fins are designed to perform equivalently.